Apr 11

Finally I decided to start a new project...

Project? What project? Click here to learn more.

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Apr 11

Hello there, today I will introduce you my brand new Altera DE1 FPGA Development Board.

Yeah! This board substitutes my Xilinx Spartan 3AN for a while, due to difficults in RAM usage (DDR2) of this board and lacking for other features (decent audio DAC, SRAM, SD slot,...).

Altera DE1 has many good and interesting features like:

  • Cyclone II EP2C20F484C7 (18,752 Logic Elements, 52x M4K 4kbits ram blocks, 234kbits embedded memory, 26x 18-bit x 18-bit multipliers, 4 PLL, 315 I/O pins)
  • EPCS4 4-Mbit serial configuration device programmable to store the FPGA configuration autoloaded on start
  • 512KByte SRAM (256x16bit asynchronous, very very useful and simple to program)
  • 8MB DRAM (synchronous DRAM but not hard-to-use as DDR2 one)
  • 4MB Flash RAM
  • 1x 50Mhz Clock
  • 1x 27Mhz Clock
  • 1x External SMA clock input
  • 12bit VGA DAC (4096 colors on screen is enough for many things)
  • 24bit Audio CODEC with lin-out, line-in, mic-in connectors (wow! how many beautiful things can we do with a similar audio DAC!!!)
  • Onboard SD card slot (yeah! useful to access external data like... ROMS....)
  • PS/2 keyboard connector
  • 10 red LEDs, 8 green LEDs, 10 switches
  • 4x debounced pushbuttons
  • 4x 7-segments display
  • 2x IDE expansion headers to accessing external devices/resources
  • 1x RS-232 (useful to monitor/debug application from PC)

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Apr 10

This time I modified VGA routines in order to drive my LCD TV correctly.

Correct VGA pixel clock is 25.175MHz but every TV hooks 25MHz correctly, so I can use my 50MHz Spartan 3AN clock without use of DCMs.

640x480 pixel are available on screen and can be managed without restrictions.

The "A" character pattern is held as LUT as 8x8 bits using distributed ram.

Two of the available switches of board is used to switch double width/height.


640x480 Normal (HiRes Mode)


640x240 Vertical Doubled (MidRes mode)


320x240 Horizontal/Vertical Doubled (LowRes Mode)



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Apr 10

Here’s my second attempt to enter FPGA world!

This time I coded (VHDL) the routine to drive the VGA output of my Xilinx Spartan 3AN.

My VGA TV handles the screen resolution correctly showing the 640×480 on-screen message.

No LUT are used and no memory allocated as framebuffer.

The routines drives the VGA output directly!

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Apr 10

Here’s my first try in FPGA programming world.

I used the T80 core got from OpenCores.org that simulates a Zilog Z80 cpu.

My ASM (Z80) routines drives the LCD display (Sitronix ST7066U) of my Xilinx Spartan 3AN board, showing the “SEGA SC-3000” message on lcd screen.


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Apr 10

90 bpm of slow-ssilation…



Apr 10


More more more acid than before!!!

Thiz shitty piece of hardware is funny!!! :)


Apr 10



Apr 10

Here’s for you my first live session with my brandnew Kaossilator synthesizer from Korg.

Let the Kaossimilation begin!


Apr 10

Anotha fuckn refunkd sht. Muzak from Kraftwerk.

Sony Vegas.