Jun 13


Finally an almost stable implementation of FAT32 filesystem in SD-5000 integrated sdcard interface.


Sep 19

This is my first beta version of the TMS9928 VDP Mode 2 implementation.
Sprites are not finished yet, so not included.
System main clock is 21,42857 Mhz (50 * 3 / 7) but VGA is running at 25Mhz.
A line-based buffering allows the clock synchronization.

SDcard loader are faster now using MasterClock / 2,
but it's track based and no FAT is supported yet.
The video shows the system startup 2 times in order to underline the new SD loader speed.



Sep 17


This time your eyes are pleasured by my first attempt to recreate SEGA SC-3000 home computer (1983).

Through this video you can see my IPL rom loading original SEGA BasicLevel 3A from SDcard.

After loading 32KB of data into RAM, the IPL rom deactivate itself rebooting into loaded data.



Jul 18

This time my Altera DE1 hosts 5 complex components:

1) Clock engine that uses an onboard PLL. It supply the MasterClock at 21,428Mhz, the SDRAM/Controller clock at  85,712Mhz and VGA clock at 25Mhz.

2) Z80 cpu core (T80SE core) running at a fraction of original 3,58Mhz and uses the Altera DE1 onboard SDRAM as RAM/ROM source.
The assembler program starts copying itself into RAM (SDRAM) at $E000 then jump to that address.
Then copy the characters bitmap data into RAM used by VDP core at $A800 (VRAM).
After this it change row by row the name table at address $A000 that VDP uses as tile number source. 

3) A simple tile-based VDP controller that uses the same SDRAM as nametable (tile numbers) and tiletable (tile bitmap data).
The VDP core uses the MASTERCLOCK as clock source and the image resolution is 288x240.
The pixel-clock is 5,357Mhz (MASTERCLOCK/4).
It prefetches 8 pixels of data in order to avoid the trace flickering.

4) Double buffered 25Mhz VGA scaler that transforms the VDP created data and adds lateral black border.
The engine manages VGA screen at 640x480 pixel doubling also the pixel size.

5) Dual port SDRAM controller that manage onboard SDRAM chip (Zentel A3V64S40ETP).
The controller it used as RAM access arbiter between CPU and VDP.
It's clocked at 85,712Mhz (MASTERCLOCK x 4). Only auto-precharged/one-burst-length access are used (READA/WRITA).
Any access is served in 8 SDRAM clocks producing 10Mhz bandwith that are shared between CPU and VDP engines.


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Jul 04

My low-level UART / RS232 routines are almost ready.

It uses 115200/8N2 (11 bits for each byte) as parameters allowing a data trasfer rate of ~10KBytes/sec.


Data trasfer into the video was done using a PC with Windows 7 and a USB2Serial cable from Hama with Prolific chip.


Altera DE1 onboard UART works well!


Apr 10

Here’s my first try in FPGA programming world.

I used the T80 core got from OpenCores.org that simulates a Zilog Z80 cpu.

My ASM (Z80) routines drives the LCD display (Sitronix ST7066U) of my Xilinx Spartan 3AN board, showing the “SEGA SC-3000” message on lcd screen.


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Apr 10

90 bpm of slow-ssilation…



Apr 10


More more more acid than before!!!

Thiz shitty piece of hardware is funny!!! :)


Apr 10



Apr 10

Here’s for you my first live session with my brandnew Kaossilator synthesizer from Korg.

Let the Kaossimilation begin!