This time my Altera DE1 hosts 5 complex components:
1) Clock engine that uses an onboard PLL. It supply the MasterClock at 21,428Mhz, the SDRAM/Controller clock at 85,712Mhz and VGA clock at 25Mhz.
2) Z80 cpu core (T80SE core) running at a fraction of original 3,58Mhz and uses the Altera DE1 onboard SDRAM as RAM/ROM source.
The assembler program starts copying itself into RAM (SDRAM) at $E000 then jump to that address.
Then copy the characters bitmap data into RAM used by VDP core at $A800 (VRAM).
After this it change row by row the name table at address $A000 that VDP uses as tile number source.
3) A simple tile-based VDP controller that uses the same SDRAM as nametable (tile numbers) and tiletable (tile bitmap data).
The VDP core uses the MASTERCLOCK as clock source and the image resolution is 288x240.
The pixel-clock is 5,357Mhz (MASTERCLOCK/4).
It prefetches 8 pixels of data in order to avoid the trace flickering.
4) Double buffered 25Mhz VGA scaler that transforms the VDP created data and adds lateral black border.
The engine manages VGA screen at 640x480 pixel doubling also the pixel size.
5) Dual port SDRAM controller that manage onboard SDRAM chip (Zentel A3V64S40ETP).
The controller it used as RAM access arbiter between CPU and VDP.
It's clocked at 85,712Mhz (MASTERCLOCK x 4). Only auto-precharged/one-burst-length access are used (READA/WRITA).
Any access is served in 8 SDRAM clocks producing 10Mhz bandwith that are shared between CPU and VDP engines.